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Memory Subsystem Architect (NPU)

  • Company: Bitdeer Technologies Group
  • Location: Singapore
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Bitdeer Technologies Group at a glance

bitdeer.com
  • Founded 2021
  • Employees 211
  • Ticker BTDR
BTDR 13.33 USD -3.75%

Investor research: Yahoo Finance · SEC filings

Registered as a global legal entity (LEI 2549007M2KGWVJ9XFP20, KY) — via GLEIF

Bitdeer Technologies Group (Nasdaq: BTDR) is a Singapore-headquartered crypto mining and AI cloud infrastructure company, spun out of Bitmain in 2021 by Jihan Wu. It runs large-scale compute and data centers in the U.S., Norway, and Bhutan. Recent coverage highlights a planned ~$36M advanced electronics manufacturing site in Sparks, Nevada, tied to AI and bitcoin hardware ambitions.

1,675 Wikipedia views in June 2026 — a rough gauge of public visibility.

Source: Wikipedia · LinkedIn · X

Bitdeer Technologies Group is hiring a Memory Subsystem Architect (NPU) for a full-time role based in Singapore. This position suits experienced professionals searching for Memory Subsystem Architect (NPU) jobs in Singapore or Memory Subsystem Architect (NPU) near me opportunities within Bitdeer Technologies Group careers.

About This Position

As a full-time Memory Subsystem Architect (NPU) in Singapore, you will lead the definition and refinement of memory architectures that support neural processing units. You will balance performance, power, area and bandwidth targets while collaborating across design teams. The role focuses on end-to-end ownership of the memory subsystem from concept through implementation guidance, making it ideal for candidates targeting Memory Subsystem Architect (NPU) positions near Singapore.

Your Responsibilities

  • Define memory hierarchy, interconnect and controller architectures optimised for NPU workloads
  • Analyse bandwidth, latency and power trade-offs for on-chip and off-chip memory solutions
  • Develop high-level models and micro-architectural specifications for caches, buffers and memory interfaces
  • Collaborate with system architects, RTL designers and verification teams to ensure seamless integration
  • Evaluate emerging memory technologies and protocols for suitability in next-generation NPU designs
  • Guide floor-planning, floorplan constraints and performance projection activities related to the memory subsystem
  • Document architectural decisions and present findings to cross-functional stakeholders

Requirements

  • Proven track record as a Memory Subsystem Architect (NPU) or equivalent role in advanced semiconductor design
  • Deep expertise in memory subsystems, including SRAM, DRAM, HBM and related high-bandwidth interfaces
  • Strong understanding of NPU dataflow, tensor operations and memory access patterns
  • Proficiency with architecture modelling, performance simulation and trade-off analysis tools
  • Familiarity with SoC integration, clocking, power domains and physical design considerations
  • Excellent communication skills for aligning multi-disciplinary teams
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or a related field, or equivalent practical experience

Working at Bitdeer Technologies Group

Bitdeer Technologies Group is hiring for this role and offers a supportive team environment.

How to Apply

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To apply for this job please visit bitdeer.breezy.hr.

What people say about Bitdeer Technologies Group

Recent news

Aggregated from public discussions and news; opinions are the authors’ own.

Working in Singapore

Role is based in Singapore, a dense island hub off the Malay Peninsula near the equator. Expect a global business and tech center with strong transport, dense urban living, and a regional base for APAC hardware and cloud work—not a remote post (onsite expected).

🇸🇬 Relocation safety for Singapore: Very Safevia Warnely, CC BY 4.0

National unemployment rate in Singapore: 2.8%via World Bank

GDP per capita in Singapore: $98,814via World Bank

Consumer price inflation in Singapore: 0.9% (annual) — via World Bank

Real GDP growth in Singapore: 5.0% (annual) — via World Bank

Average hours worked per week in Singapore: 46.3via ILOSTAT

    Build the skills for this role

    Prioritize NPU/accelerator architecture, memory controllers and hierarchies (cache, HBM, DDR), performance modeling, RTL/SoC co-design literacy, and power-aware system thinking. No listed cert path in source data—depth in memory subsystem papers and prior NPU/GPU/ASIC work matters more than generic badges.

    Expect deep dives on memory bandwidth vs capacity, bank conflicts, QoS for multi-tenant AI inference/training, ECC/reliability at scale, and how memory choices affect Bitdeer-style high-density compute. Prepare whiteboards on HBM stacks, NoC/memory fabric, and tradeoffs under power and cost caps.

    Strong fit if you have hands-on memory architecture for NPUs/AI accelerators and want Singapore-based work at a public mining-and-AI infra builder expanding manufacturing and silicon-adjacent capability. Thin public role data—push for team scope and tape-out stage in process.

    Job details above are provided by the employer/source. The sections on this page are compiled from public data sources with AI assistance.

    Accommodations: if you need a workplace accommodation to apply for or perform this job, see ADA.gov or EEOC.gov for guidance on your rights and how to request one.

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    Listing facts

    • Role Memory Subsystem Architect (NPU)
    • Employer Bitdeer Technologies Group
    • Location Singapore
    • Type Full Time
    • Posted July 6, 2026
    • Apply by 2026-08-09
    • Country context Singapore
    • Overview Full original description on this page (329 words; rewritten for clarity, not a teaser paste)

    Facts above come from this job record on Get A Job.AI — not copied from third-party review sites.

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    Memory Subsystem Architect (NPU) Bitdeer Technologies Group