Analog Layout Engineer (Lead)

About This Opportunity

We are representing a confidential semiconductor organization at the forefront of AI infrastructure innovation. Our client is developing advanced chiplet-based solutions that address critical challenges in AI hardware scalability and efficiency. This is an exceptional opportunity for a senior analog layout professional to join a technically ambitious team working on next-generation interconnect technology.

Responsibilities

As Lead Analog Layout Engineer, you will:

• Execute custom layout and verification of analog circuits, cells, blocks, and IP for multi-gigabit high-speed chip-to-chip communication links (SerDes up to and beyond 28Gb/s and memory IO) in advanced semiconductor process nodes
• Design layout for very high-speed analog circuits with attention to parasitic minimization, matching constraints, and signal integrity
• Collaborate closely with circuit design teams to understand requirements and implement optimal layout solutions
• Support IP and chip-level integration activities across the product development cycle
• Engage with customers on technical requirements and IP delivery milestones
• Work with flip-chip package technologies and their layout implications

What We're Looking For

Required Experience:

• Proven experience in custom analog layout of circuits and blocks for multi-gigabit serial data-link transceivers or high-frequency/RF circuits
• Expert-level layout skills for high-speed/frequency circuits including amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing circuits, buffers, regulators, filters, and data converters
• Deep understanding of layout approaches and techniques for high-speed circuits, including matching constraints, parasitic minimization, power grid design, and ESD requirements
• Hands-on experience with modern semiconductor process technologies including 28nm, 14/16nm, and 7nm nodes
• Proficiency with industry-standard EDA tools for design and verification: Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction and modeling, EM and IR drop analysis, and ESD verification

Skills and Attributes:

• Self-motivated with a strong sense of ownership and accountability
• Excellent communication skills and proven ability to work collaboratively in team environments
• Capable of managing workload and schedules independently while reporting effectively to management
• Background in semiconductor physics preferred

Education:

• Graduate degree in Electrical Engineering or related discipline

Location: Reading, UK

How We Work with You

Get A Job.ai is managing the full recruitment process for this confidential client engagement. When you apply through our platform at getajob.ai, one of our specialized technical recruiters will review your background and conduct an initial screening. If there's a strong match, we will submit your profile to our client and coordinate all interview stages on your behalf. Please do not attempt to contact the client directly, as all applications must come through our talent team to be considered.

Pay

Compensation details will be discussed during the screening process with our recruitment team and will be competitive with senior analog layout engineering roles in the UK semiconductor market.

Equal Opportunity: Get A Job.ai is committed to inclusive hiring practices. We welcome applications from all qualified candidates regardless of race, color, religion, sex, national origin, age, disability, or any other protected characteristic.