Senior DFT Power Methodology Engineer

Nvidia is actively seeking a Senior DFT Power Methodology Engineer in US, CA, Santa Clara. This full-time role centers on refining high-impact design-for-test approaches that carefully balance power efficiency with rigorous verification standards.

Position Summary

As a Senior DFT Power Methodology Engineer with Nvidia in Santa Clara, you will help define and advance refined techniques that embed power considerations into testability frameworks from the earliest design stages. The position emphasizes creating reliable, scalable methodologies that maintain high fault coverage while supporting efficient power behavior during test operations. You will work closely with cross-functional specialists to ensure that power-aware practices become seamless components of overall product readiness. Candidates ready to elevate DFT excellence in a dedicated on-site Santa Clara environment will find this full-time opportunity especially rewarding.

Core Duties

• Define and continuously improve DFT methodologies that fully incorporate power intent and multi-domain constraints.
• Partner with architecture and implementation teams to embed power-conscious scan and test-point strategies into active designs.
• Assess power profiles of generated test patterns and refine them for reduced consumption without sacrificing coverage quality.
• Build and maintain automated scripts and process flows supporting power-aware DFT insertion, analysis, and validation.
• Troubleshoot complex interactions between power modes and test circuitry, both in pre-silicon simulation and post-silicon bring-up.
• Document standards and promote consistent adoption of power-optimized DFT practices across projects.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or an equivalent technical field.
• Proven hands-on experience developing and applying DFT methodologies on large-scale designs, with particular strength in power-related aspects.
• Deep familiarity with core DFT constructs such as scan chains, compression, built-in self-test, and boundary scan together with UPF-style power specification.
• Working knowledge of leading commercial EDA platforms for DFT generation, simulation, and power analysis.
• Demonstrated ability to isolate and resolve power-domain conflicts that appear under test conditions.
• Clear written and verbal communication skills that support productive collaboration inside multidisciplinary engineering groups.

Why Join Nvidia

Nvidia is hiring for this role and offers a supportive team environment where the Senior DFT Power Methodology Engineer can contribute meaningfully while advancing specialized skills in Santa Clara.

Next Steps

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