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Be ready to walk through DFT architectures you owned, power-related test failures you diagnosed, methodology tradeoffs (coverage vs. power vs. pattern volume), and how you drove adoption of a flow across teams. Expect scenario questions on debug, tool chain limits, and communication with design and product groups.
Strong fit if you already lead DFT or power-test methodology on large digital chips and want impact at a GPU/AI silicon company headquartered in Santa Clara. Less fit if you prefer pure RTL design, fully remote work, or roles without methodology ownership.
As a Senior DFT Power Methodology Engineer at Nvidia, expect to define and refine design-for-test flows aimed at power-aware silicon validation for GPU/SoC-class products. Typical work: methodology specs, power-focused DFT patterns and analysis, cross-team reviews with design/DFT/power groups, and tooling or flow improvements so test coverage and power behavior stay aligned through tapeout-oriented milestones.
No cert catalog was provided. Prioritize deep DFT (scan, ATPG, BIST), power-aware test/methodology, EDA flows, and clear technical writing for methodology docs. Hands-on silicon bring-up and cross-functional influence matter more here than generic certificates.
The listing marks remote as off and places the job in Santa Clara, CA, so plan for on-site or hybrid expectations unless Nvidia states otherwise later.
GPUs, SoCs, and related software stacks for AI, HPC, and other compute markets—so DFT power methodology supports complex, power-sensitive silicon.
No certification resources were supplied for this occupation family; strength of relevant silicon DFT and power experience is the practical signal.
Website: nvidia.com
Nvidia Corporation is an American multinational technology company headquartered in Santa Clara, California. The company develops graphics processing units (GPUs), systems on chips (SoCs), and application programming interfaces (APIs) for data science, high-performance computing, artificial intelligence (AI), and mobile and automotive applications. Founded in 1993 by Jensen Huang, Chris Malachowsky, and Curtis Priem, Nvidia has been widely described as a Big Tech company.
Public cache only — not an employee review.
Nvidia is actively seeking a Senior DFT Power Methodology Engineer in US, CA, Santa Clara. This full-time role centers on refining high-impact design-for-test approaches that carefully balance power efficiency with rigorous verification standards. Position Summary As a Senior DFT Power Methodology Engineer with Nvidia in Santa Clara, you will help define and advance refined techniques that embed power considerations into testability frameworks from the earliest design stages. The position emphasizes creating reliable, scalable methodologies that maintain high fault coverage while supporting efficient power behavior during test operations. You will work closely with cross-functional specialists to ensure that power-aware practices become seamless components of overall product readiness. Candidates ready to elevate DFT excellence in a dedicated on-site Santa Clara environment will find this full-time opportunity especially rewarding. Core Duties Define and continuously improve DFT methodologies that fully incorporate power intent and multi-domain constraints. Partner with architecture and implementation teams to embed power-conscious scan and test-point strategies into active designs. Assess power profiles of generated test patterns and refine them for reduced consumption without sacrificing coverage quality. Build and maintain automated scripts and process flows supporting power-aware DFT insertion, analysis, and validation. Troubleshoot complex interactions between power modes and test circuitry, both in pre-silicon simulation and post-silicon bring-up. Document standards and promote consistent adoption of power-optimized DFT practices across projects. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or an equivalent technical field. Proven hands-on experience developing and applying DFT methodologies on large-scale designs, with particular strength in power-related aspects. Deep familiarity with core DFT constructs such as scan chains, compression, built-in self-test, and boundary scan together with UPF-style power specification. Working knowledge of leading commercial EDA platforms for DFT generation, simulation, and power analysis. Demonstrated ability to isolate and resolve power-domain conflicts that appear under test conditions. Clear written and verbal communication skills that support productive collaboration inside multidisciplinary engineering groups. Why Join Nvidia Nvidia is hiring for this role and offers a supportive team environment where the Senior DFT Power Methodology Engineer can contribute meaningfully while advancing specialized skills in Santa Clara. Next Steps To apply, complete your…
Generated for personal interview prep · 2026-07-16 UTC · getajob.ai