Senior Mixed-Signal Verification Engineer

About This Opportunity

We are representing a confidential semiconductor technology company working at the cutting edge of processor design. Our client is backed by leading deep-tech investors and industry veterans, and they're building breakthrough systems that address the performance demands of modern AI workloads.

We're seeking a Senior Mixed-Signal Verification Engineer to join their Paris-based team. This role offers ownership of critical verification methodology and the chance to work on complex digital-to-analog interfaces at the heart of next-generation chip architectures.

Responsibilities

• Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on advanced systems-on-chip
• Build and maintain verification environments at block, subsystem, and SoC level
• Develop tests, assertions, checkers, scoreboards, and functional coverage
• Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions
• Run regressions, analyze coverage, debug failures, and drive verification to sign-off
• Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation
• Collaborate closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues

What We're Looking For

Required qualifications:

• Strong hands-on experience in ASIC or SoC verification
• Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces
• Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology
• Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage
• Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts
• Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior
• Experience with scripting and automation, preferably Python, Tcl, shell, or similar
• Proficient English language skills

Preferred qualifications:

• Verification experience with complex high-speed interface IP such as PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar PHY-based interfaces
• Experience verifying interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or other digital/analog control loops
• Experience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, or equivalent mixed-signal verification techniques
• Experience developing or integrating behavioral models of analog/PHY components into digital verification environments
• Experience with SoC-level integration and verification of complex interface IP
• Experience with low-power verification, power-state management, or UPF
• Experience driving a complex IP or SoC verification effort through coverage closure and tape-out

How We Work With You

When you apply through Get A Job.ai, our recruiting team will review your profile and arrange an initial screening call. If there's a strong match, we'll submit your candidacy to our client and guide you through their interview process. Please do not contact the client directly—all communication should flow through our team to ensure the best outcome for your application.

Pay and Benefits

Our client offers competitive cash compensation based on location, experience, and internal equity. The majority of full-time offers include a meaningful stock option plan. Benefits include healthcare coverage with family-friendly options, pension contributions, professional development support, and 25 days of paid time off in addition to public holidays. You'll have ownership of a key technical domain with significant growth opportunities based on performance.

Location: Paris, France

Get A Job.ai is an equal opportunity recruiter. We welcome applications from candidates of all backgrounds and work to ensure fair and inclusive hiring processes for the organizations we represent.