Design for Test (DFT) Engineer, Principal

Positron.ai is seeking a Principal Design for Test (DFT) Engineer to guide test architecture strategy and execution for our advanced AI inference accelerators, located in the United States.

Role Overview

As Principal DFT Engineer, you'll drive end-to-end testability strategy across the complete ASIC development lifecycle for our inference platform. This position combines technical leadership and hands-on implementation, spanning test methodology architecture, RTL and vendor IP integration, collaboration with design services partners, and validation through first silicon. You'll set company-wide test design standards and ensure testability is embedded from architecture conception through production silicon.

Key Responsibilities

• Establish long-term testability and design-for-manufacturability roadmaps supporting product quality, yield enhancement, production screening efficiency, and field diagnostics
• Architect and implement comprehensive test infrastructure—scan-based methodologies, data compression techniques, built-in self-test for memory and logic, IEEE 1149.x compliance, IEEE 1687 debug frameworks, and silicon observability features
• Integrate test methodology into all internal RTL development and assess test capabilities available from third-party IP blocks
• Create and execute DFT validation strategies, confirm coverage through simulation and gate-level analysis, and drive multiple ATPG fault coverage approaches including design-rule checking, stuck-at faults, dynamic behavior, device-aware, and power-constrained scenarios
• Work with backend teams to translate test architecture into physical layout, optimizing scan organization, compression schemes, timing performance, and low-power test execution
• Provide technical oversight for all DFT work performed by external design partners, including quality assessment, review of implementation details, and acceptance criteria definition
• Lead cross-team coordination with RTL engineers, functional verification specialists, layout teams, packaging engineers, test manufacturers, embedded firmware developers, and silicon validation specialists
• Incorporate contemporary AI engineering tools and methodologies to accelerate DFT processes, including intelligent report analysis, optimization algorithms, coverage enhancement, and engineering workflow automation

What You Bring

Required Qualifications:

• Bachelor's, Master's, or Doctoral degree in Electrical Engineering or Computer Engineering
• 12 or more years of professional experience in ASIC design and development
• Substantial hands-on track record implementing test methodologies for highly complex integrated circuits, including multiple successful commercial tapeouts
• Thorough technical knowledge of scan design patterns, automatic test pattern generation, memory test algorithms, logic self-test approaches, IEEE boundary standards, inter-chip debug protocols, test data reduction, fault classification, and coverage measurement
• Working proficiency with industry-standard test design tools such as Siemens Tessent, Synopsys TestMAX DFT, Cadence Modus, or comparable platforms
• Expert-level RTL design capabilities using Verilog and SystemVerilog
• Hands-on experience with synthesis tools and gate-level simulation environments
• Demonstrated proficiency in scripting languages including Python, Tcl, Perl, or equivalent tools
• Advanced debugging expertise spanning register-transfer level, gate-level netlists, and silicon-level fault analysis
• Proven success directing and aligning cross-disciplinary technical teams toward shared engineering objectives

Preferred Qualifications: Experience with AI inference accelerators, GPUs, CPUs, or networking silicon; PCIe, HBM, and mobile memory architectures; chiplet-based system design; high-speed differential signaling on advanced process nodes below 5nm; power-aware circuit optimization and yield engineering; silicon debugging and post-silicon troubleshooting; security-aware manufacturing procedures; in-system debug and observability architecture; emulation platforms such as Palladium, ZeBu, Veloce, or FPGA-based prototyping; and coherent multi-vendor IP integration strategies.

About the Company

Positron.ai develops specialized hardware acceleration solutions engineered specifically for artificial intelligence inference workloads. Our systems deliver superior performance efficiency and economics relative to conventional GPU-based approaches, achieving measurable gains in throughput per investment and power consumption per computation. Our mission is to create the industry-leading inference computing platform.

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