Ground every answer in facts on this page and the original listing. We never invent Glassdoor-style reviews or salaries that are not in our data.
Website: positronai.com
Public cache only — not an employee review.
Positron.ai is seeking a Principal Design for Test (DFT) Engineer to guide test architecture strategy and execution for our advanced AI inference accelerators, located in the United States. Role Overview As Principal DFT Engineer, you'll drive end-to-end testability strategy across the complete ASIC development lifecycle for our inference platform. This position combines technical leadership and hands-on implementation, spanning test methodology architecture, RTL and vendor IP integration, collaboration with design services partners, and validation through first silicon. You'll set company-wide test design standards and ensure testability is embedded from architecture conception through production silicon. Key Responsibilities Establish long-term testability and design-for-manufacturability roadmaps supporting product quality, yield enhancement, production screening efficiency, and field diagnostics Architect and implement comprehensive test infrastructure—scan-based methodologies, data compression techniques, built-in self-test for memory and logic, IEEE 1149.x compliance, IEEE 1687 debug frameworks, and silicon observability features Integrate test methodology into all internal RTL development and assess test capabilities available from third-party IP blocks Create and execute DFT validation strategies, confirm coverage through simulation and gate-level analysis, and drive multiple ATPG fault coverage approaches including design-rule checking, stuck-at faults, dynamic behavior, device-aware, and power-constrained scenarios Work with backend teams to translate test architecture into physical layout, optimizing scan organization, compression schemes, timing performance, and low-power test execution Provide technical oversight for all DFT work performed by external design partners, including quality assessment, review of implementation details, and acceptance criteria definition Lead cross-team coordination with RTL engineers, functional verification specialists, layout teams, packaging engineers, test manufacturers, embedded firmware developers, and silicon validation specialists Incorporate contemporary AI engineering tools and methodologies to accelerate DFT processes, including intelligent report analysis, optimization algorithms, coverage enhancement, and engineering workflow automation What You Bring Required Qualifications: Bachelor's, Master's, or Doctoral degree in Electrical Engineering or Computer Engineering 12 or more years of professional experience in ASIC design and development Substantial hands-on track record implementing test methodologies for highly complex integrated circuits, including multiple successful commercial tapeouts Thorough technical knowledge of scan design patterns, automatic test pattern generation, memory test algorithms, logic self-test approaches, IEEE boundary standards, inter-chip debug protocols, test data reduction, fault classification,…
Generated for personal interview prep · 2026-07-18 UTC · getajob.ai