Senior Principal ASIC Design Engineer

Responsibilities

Our talent team is representing a confidential semiconductor organization developing advanced connectivity solutions for next-generation AI infrastructure. We are seeking a Senior Principal ASIC Design Engineer to provide senior technical leadership driving chip design for high-speed networking products.

You will define technical direction across the complete ASIC design flow, spanning high-speed Ethernet, advanced interconnect protocols, and PCIe Gen 6/7 implementations. Your work will solve complex scale-up networking challenges while mentoring senior engineers and transforming ambitious product goals into production-ready silicon.

Technical Leadership & Architecture:

• Define and drive ASIC architecture for connectivity products across multiple high-speed protocols and AI interconnect fabrics
• Lead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and network fabrics
• Define scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control
• Architect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads
• Lead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability
• Serve as technical authority across digital, networking, and system domains

ASIC Design & Execution:

• Lead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and networking subsystems
• Design packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces
• Develop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration
• Design scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service
• Partner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics
• Drive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up
• Partner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets

What We're Looking For

Required Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 12+ years of ASIC/SoC design experience with a proven track record delivering complex, high-speed networking or connectivity silicon from architecture through production
• Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs
• Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems
• Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies
• Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration
• Strong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics
• Hands-on experience across the complete ASIC development flow: architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation
• Demonstrated technical leadership across multiple teams and product programs

Preferred Qualifications:

• Master's or PhD in Electrical Engineering, Computer Engineering, or related technical discipline
• Direct experience with advanced interconnect protocols including PCIe Gen 6/7 and advanced Ethernet architectures
• Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines
• Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems
• Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts
• Excellent communication, collaboration, and mentorship skills

Location: Remote (Germany-based preferred for team collaboration)

How We Work With You

Candidates apply directly through Get A Job.ai. Our recruiting team will conduct an initial screening to understand your background and match it to our client's requirements. We will then submit qualified candidates to the client for their interview process. Please do not contact the client directly—all communication and coordination will flow through Get A Job.ai to ensure the best candidate experience.

Pay

Compensation details will be discussed during the screening process and are competitive for senior principal-level ASIC design roles in the semiconductor industry.

Get A Job.ai is an equal opportunity recruiter. We encourage applications from candidates of all backgrounds and experiences, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.