Senior Director System Validation Engineer

Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

• Seeking a strong technical leader who has delivered multiple SoC products.
• Lead and scale the system validation organization for Astera Labs’ AI fabric portfolio, building a high-performing team across multiple concurrent product programs.
• Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs’ connectivity products for AI and ML applications.
• Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification.
• Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.
• Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.
• Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness.
• Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs’ solutions.
• The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.
• Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies.
• Drive a culture of technical excellence, accountability, and continuous improvement.
• Manage resource planning, and vendor/partner relationships.

Basic Qualifications

• Strong academic background in Electrical or Computer Engineering. Bachelor’s required, Master’s preferred.
• ≥15 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.
• ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• ≥5 years building high performance Engineering teams and validation methodologies.
• Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.
• Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.
• Strong background in debug methodologies, lab infrastructure, and automation frameworks.
• Excellent communication skills and ability to influence executives and cross‑functional partners.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!

Preferred Experience

• ≥8 years leading validation teams planning, execution and maintaining project visibility.
• ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems.
• Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet.
• Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence.

The base salary range is $240,000 USD – $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.