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Expect deep DV fundamentals: UVM components, scoreboarding, coverage closure, race/debug stories, and architecture-aware corner cases. Be ready to walk through a past block you verified end-to-end and how you drove sign-off quality at staff scope.
Strong fit if you already lead verification on complex RTL (CPU, interconnect, or large IP), enjoy methodology and mentorship, and want on-site work in Bengaluru’s chip ecosystem with a RISC-V-focused employer.
A typical day for Staff / Sr. Staff Engineer DV at SiFive centers on verification planning for RISC-V cores or SoC blocks: reviewing RTL, defining coverage and testbench strategy, debugging failing sims/UVM regressions, mentoring junior DV engineers, and aligning with design and architecture on bug severity and tapeout readiness.
Prioritize SystemVerilog/UVM, constrained-random and coverage-driven verification, assertion-based checks, waveform debug, and familiarity with CPU/SoC concepts (caches, interconnects, privilege modes). RISC-V ISA knowledge is a strong differentiator for SiFive-style work.
No—the listing is for Bengaluru, Karnataka, India (on-site / non-remote).
Design verification: proving RTL/IP correctness with simulation, UVM testbenches, coverage, and sign-off—not product QA or software test.
No certification list was provided for this posting; hiring typically emphasizes hands-on DV depth over vendor certs.
Website: sifive.com
Public cache only — not an employee review.
Join Sifive as a Staff / Sr. Staff Engineer DV in Bengaluru, Karnataka, India, where you will contribute to cutting-edge semiconductor design verification projects. What This Role Involves This position focuses on the development and implementation of digital verification methodologies for complex SoC designs. As a Staff / Sr. Staff Engineer DV, you will lead the creation and execution of comprehensive test plans to ensure product reliability and performance. Responsibilities Design and develop verification environments for digital circuits and systems. Create and maintain testbenches, assertions, and coverage models. Collaborate with cross-functional teams to define verification requirements and strategies. Analyze and debug complex hardware issues using simulation and emulation tools. Mentor junior engineers and provide guidance on best practices in digital verification. Requirements A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. Minimum of 8 years of experience in digital verification for SoCs. Expertise in verification languages such as SystemVerilog, UVM, and OVM. Strong understanding of digital design principles and verification techniques. Experience with emulation and formal verification tools is highly desirable. Excellent problem-solving skills and the ability to work effectively in a team environment. About the Company Sifive is hiring for this role and offers a supportive team environment. We are committed to fostering innovation and providing our employees with opportunities to grow professionally. How to Apply To apply, complete your application directly on this page, or you'll be redirected to the employer's application platform to finish submitting there.
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