Mercor
Mercor is seeking a RTL Design Engineer – AI Tools to evaluate and enhance AI model training for digital chip design and verification, with a compensation of $100–$175/hour.
Requirements
- 3–10 years of experience in digital RTL design or design verification.
- Strong proficiency in Verilog/SystemVerilog and UVM.
- Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
- Experience with ASIC design flows and EDA tools.
- Familiarity with leveraging LLM-based tools for chip design and verification workflows.
Benefits
- Career growth opportunities
- Opportunities for professional development
- Access to top-notch resources and support
Originally posted on Himalayas
To apply for this job please visit himalayas.app.
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