Advanced Packaging Process Engineer III E3)

Applied Materials is seeking a full-time Advanced Packaging Process Engineer III (E3) to join its semiconductor technology team in Santa Clara, California — at the center of the global electronics supply chain.

About the Role

As a recognized leader in materials engineering, Applied Materials drives the innovation behind virtually every advanced chip and display manufactured today. In this senior individual-contributor role, you will develop, optimize, and qualify next-generation packaging processes on cutting-edge capital equipment, working at the intersection of materials science, device physics, and manufacturing scale-up.

What You'll Do

• Own end-to-end process development and optimization for advanced packaging technologies including fan-out wafer-level packaging (FOWLP), 2.5D/3D IC integration, chiplet interconnects, and through-silicon vias (TSV)
• Design and execute structured experiments (DOE) to characterize process windows, establish control limits, and drive yield improvement
• Lead root-cause analysis and failure investigation using physical and electrical characterization techniques
• Develop and maintain detailed process specifications, traveler documentation, and SPC monitoring plans
• Partner with equipment engineers, R&D teams, and customer application engineers to support tool qualification, process transfer, and technology ramps
• Analyze process data using statistical tools to identify trends, correlations, and continuous-improvement opportunities
• Contribute technical expertise during customer demos, evaluations, and joint-development programs

What We're Looking For

• Bachelor's, Master's, or Ph.D. in Materials Science, Chemical Engineering, Electrical Engineering, or a closely related discipline
• Demonstrated hands-on experience in semiconductor or advanced packaging process engineering (deposition, etch, CMP, lithography, or interconnect processes)
• Practical knowledge of advanced packaging architectures such as CoWoS, SoIC, flip-chip, or embedded die technologies
• Proficiency with statistical analysis and DOE methodologies (JMP, Minitab, or equivalent)
• Comfortable operating in a cleanroom environment and interpreting metrology and inspection data
• Strong written and verbal communication skills; able to translate complex technical findings for cross-functional audiences
• Self-directed and effective in a collaborative, fast-paced engineering organization

About Applied Materials

Applied Materials is the global foundation of the semiconductor and display industry, engineering the equipment and process solutions that make modern electronics possible. From logic and memory to advanced packaging for AI and high-performance computing, Applied's innovations power the devices the world depends on. The Santa Clara headquarters puts you at the heart of Silicon Valley's most consequential technology work.

How to Apply

Ready to advance your career as an Advanced Packaging Process Engineer in Santa Clara? Submit your application directly through this listing to be considered for this full-time opportunity with Applied Materials.